Title: What is the role of the interfaces in AI hardware?
Abstract: In today’s rapidly evolving technology landscape, the rivalry between AMD’s UALink and NVIDIA’s NVLink is far more than a competition between interconnect architectures—it marks a unique moment of opportunity for anyone aspiring to build a career in Analog and RF IC Design. And the ecosystem is expanding even further: Qualcomm is preparing to enter the race with the Ai200/Ai250, accelerating the pace of innovation. But how do these AI megatrends connect to the future of Analog/RF engineers? The answer lies at the heart of every next-generation AI accelerator (not CPU and GPU): the High-Speed Physical Interface (PHY). Whether in NVLink, UALink or Ai250, these interfaces push data at hundreds of gigatransfers per second per lane, demanding the most advanced Analog/RF design techniques available today. Designing these PHYs requires mastery across a broad spectrum of circuits and systems, including high-linearity drivers and receivers, sophisticated equalization schemes (CTLE, DFE, FFE), high-frequency clock generation and PLLs, ultra-fast SerDes architectures, and strategies for maintaining signal integrity across advanced PCBs and cutting-edge packaging. This keynote revisits the foundational principles of PHY design, with a spotlight on its signal-processing core, and concludes with intuitive high-level examples of how CTLEs and DFEs are architected. Ultimately, the talk highlights a powerful message: the future success of AI data centers depends fundamentally on Analog/RF IC Design, and the demand for engineers in this field is about to surge like never before.
Biography: Pedro Toledo is a Staff Analog Design at Synopsys, Lisbon, where he works in the development of high-speed SerDes and equalization circuits in advanced CMOS technologies, including nanosheet, GAA, and FinFET. His work focuses on PHY building blocks for PCIe, USB, and MPHY interfaces, covering CTLE, DFE, CDR, LDO, and signal-detection circuits. He received the Ph.D. degree in Microelectronics from Politecnico di Torino, Italy, and the Federal University of Rio Grande do Sul (UFRGS), Brazil, where he graduated Summa Cum Laude. His research interests include DIGOTA architectures, ZTC/GZTC MOSFET modeling, low-voltage analog design, and digital-based analog processing. Dr. Toledo has authored numerous papers in IEEE journals and conferences and serves as reviewer for several IEEE Transactions and Letters. He is the recipient of multiple awards, including the SBMicro Best PhD Thesis Award, the IEEE ICECS Best Student Paper Award, and the YEF-ECE Best Paper Award.