Tutorials

As the demand for more powerful and efficient custom chips continues to rise, there is an increasing need for experienced and knowledgeable chip designers. However, analog design remains a “black art” that requires years of practice to master. The increased complexity of transistor models has aggravated the problem and widened the gap between simple analytical models and (post-layout) simulation results. Consequently, the design process is tending towards a trial-and-error process on simulation tools, which calls for a new paradigm for analog IC design that restores the designer’s intuition, boosts productivity, and makes analog IC design a systematic and optimized process. The use of precomputed look-up tables (LUTs) to enable intuitive and visualized design scenarios is a promising candidate for this new design paradigm. This tutorial will provide insights in using precomputed LUTs to redefine sizing at the device and circuit level. We will explain how LUTs can capture the effective parameters of an arbitrary device using black box characterization. Next, we will see how the LUTs can be used to enable sizing the devices using their electrical parameters instead of using the geometry. Finally, we will see practical design examples for design space exploration, interactive sensitivity analysis, feasibility studies, and what-if scenarios for several analog building blocks.

Flexible and multimodal sensors are transforming modern electronics, driving advances in smart healthcare, wearable monitoring, Industry 4.0, and the Internet of Things. Yet, current approaches to sensor chip development remain fragmented. Application-Specific Integrated Circuits (ASICs) provide high accuracy and efficiency but are costly and limited to niche applications, while general-purpose solutions such as FPGAs and microcontrollers offer adaptability at the expense of miniaturization, power efficiency, and multifunctionality.

This tutorial introduces a new design paradigm: Universal Multimodal Actuator Sensor Chips (UMASCs). These platforms combine the precision of ASICs with the versatility of programmable solutions, enabling circuits that operate across multiple sensing and actuation modalities. UMASCs achieve universality along two dimensions: circuit functionality and form factor adaptability. On the circuit level, UMASCs leverage reconfigurable building blocks—such as amplifiers, OTAs, ADCs, DACs, filters, and waveform generators—that can be reused across electrophysiological, electrochemical, optical, and mechanical measurements. On the physical level, they can be implemented in bulk CMOS, ultra-thin chips, hybrid systems-in-foil, or through integration with organic and printed non-organic transistors.

In the beginning a review of flexible and organic electronics is presented, establishing the foundations of materials, fabrication techniques, and circuit design challenges. The UMASC framework is then discussed, including its design requirements, building blocks, and technical feasibility in mature CMOS technologies. Case studies will highlight applications in biomedical implants (electrophysiology, neurostimulation, impedance spectroscopy), biosensors (glucose, oxygen, pH), wearable optical monitoring (PPG, NIRS), and IoT/industrial sensing (flexible smart labels, multimodal monitoring). Participants will gain both a conceptual understanding and a practical methodology for designing universal multimodal sensor platforms that are future-ready, adaptable, and scalable. The tutorial is intended for engineers, researchers, and graduate students working in circuit design, sensors, biomedical electronics, and emerging flexible technologies.

This tutorial provides a comprehensive introduction to the design and implementation of low-power analog hardware classifiers tailored for machine learning (ML) applications, with a focus on energy-constrained environments such as edge devices and biomedical wearables. With the growing need for fast, efficient, and real-time data processing, analog computing has re-emerged as a promising solution that enables in-memory computation and significantly reduces power consumption compared to conventional digital processors.

The tutorial is designed to guide participants from fundamentals to practical deployment, starting with an overview of analog signal processing principles, followed by an in-depth discussion of circuit-level implementations operating in the sub- threshold region and architectural design of classifiers such as Bayesian classifier, Voting classifier, Gaussian mixture model and Support vector machines. Emphasis is placed on understanding the power-performance trade-offs, the impact of non- idealities, noise resilience, and techniques for enhancing linearity and dynamic range in analog circuits.

Hands-on case studies based on real-life classification tasks (e.g., thyroid disease detection, ECG signal analysis, image edge detection) will be presented using Python, Cadence Virtuoso simulation tools and software-hardware codesign architectures. In addition, the tutorial provide an analysis related to hybrid analog- digital systems, training-aware hardware co-design, and prospects for reconfigurable analog machine learning chips.

This tutorial targets researchers, graduate students, and engineers interested in analog/mixed-signal IC design, edge ML systems, and energy-efficient hardware. Attendees will gain both theoretical insights and practical know-how to design analog classifier architectures that meet the demands of next-generation AI applications.

The growing computational demands of machine learning (ML) have driven the development of specialized hardware accelerators. Among these, Field-Programmable Gate Arrays (FPGAs) have emerged as an ideal platform due to their reconfigurability, energy efficiency, and ability to achieve low-latency processing. FPGAs enable the customization of ML accelerator architectures to match specific application requirements, making them a preferred choice in domains such as autonomous systems, healthcare, and data analytics.

Despite their advantages, designing and verifying ML accelerators on FPGAs is inherently challenging. Engineers must navigate complex hardware-software co-design, optimize for limited resources, and rigorously verify functionality to ensure reliable operation. These challenges are compounded by the increasing demand for shorter development cycles and the need for more efficient workflows. Traditional manual design and verification approaches, while effective, are time-consuming and prone to human error.

This tutorial explores the transformative potential of AI-assisted workflows, specifically those leveraging Large Language Models (LLMs), to address these challenges. LLMs can assist in Hardware Description Language (HDL) generation, error detection, and verification, enabling designers to streamline development and reduce debugging time. This integration of manual expertise with AI-driven assistance represents a paradigm shift in FPGA-based ML accelerator design and verification.

The tutorial will begin by establishing the relevance of FPGAs in ML acceleration and the associated challenges of manual workflows. Participants will gain foundational knowledge in designing ML accelerators using manual methods, including optimization techniques and verification strategies. The session will then transition to an in-depth exploration of AI-assisted workflows, highlighting how LLMs can enhance HDL generation, optimize designs, and improve verification accuracy. Practical demonstrations and real-world case studies will illustrate the benefits and limitations of integrating LLMs into FPGA development.

By the end of the tutorial, participants will understand how to combine traditional and AI- assisted techniques to address the complexities of FPGA-based ML accelerator design. They will gain actionable insights into implementing efficient, reliable, and scalable hardware solutions that meet the demands of modern ML workloads. This tutorial is particularly valuable for hardware designers, researchers, and industry practitioners seeking innovative approaches to accelerate their workflows and improve design outcomes.