Hands-on Workshop on Chip Design and Fabrication

From Idea to Manufactured Silicon: A 2-Day Intensive Open-Source ASIC Design Flow

Date

December 9-10, 2026

Location

Borneo Cultures Museum, Kuching, Sarawak, Malaysia

Co-located with

38th IEEE International Conference on Microelectronics (ICM 2026)

Format

2-Day, Hands-on, Beginner-friendly

Capacity

Limited to 60 Selected Participants

Key Benefit

Qualifying designs will be fabricated into a physical chip via Tiny Tapeout & Open Silicon Initiative!

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Workshop Overview & Highlights

This intensive two-day workshop introduces participants to the complete open-source digital integrated circuit (IC) design flow, combining transistor-level implementation with an automated RTL-to-GDSII workflow


Starting with an overview of the global IC ecosystem and open-source Process Design Kits (PDKs), participants will learn about community-driven ASIC fabrication initiatives like Tiny Tapeout, UNIC-CASS, Chipathon, and Code-A-Chip

Hands-On Experience

Transistor-Level Design

Implement a Boolean function from schematic simulation through layout, LVS, parasitic extraction (PEX), and post-layout verification.

Verilog & Automated RTL-to-GDSII

Develop and simulate a 4-bit counter in Verilog, pushing it through a full automated digital ASIC flow using open-source EDA tools.

Tapeout Integration

Integrate your design into the Tiny Tapeout platform for real-world chip manufacturing.

Key Learning Outcomes

  • Understand the Ecosystem Navigate the global integrated circuit landscape, open-source PDKs, and community tapeout programs (Tiny Tapeout, Chipathon, Code-A-Chip, UNIC-CASS).
  • Transistor-Level Implementation Build and verify a Boolean function from schematic through layout design.
  • Physical Verification Execute Layout Versus Schematic (LVS) checks, Parasitic Extraction (PEX), and post-layout simulations.
  • Digital Design & Simulation Write, test, and simulate digital logic (4-bit counter) in Verilog.
  • RTL-to-GDSII Automation Execute an automated open-source EDA digital flow.
  • Silicon Fabrication Readiness Package and submit finished designs to the Tiny Tapeout platform ready for manufacturing.

Program & Schedule

Featured Instructor: Juan Sebastian Moya, International Iberian Nanotechnology Laboratory (INL)

DAY 1: Ecosystem, Concepts & Schematic Simulation

Time Session Title & Details
08:30 – 09:30 Opening Session & Introduction
09:30 – 10:30 Global IC Ecosystem
Commercial organization of the world's integrated circuit ecosystem
10:30 – 12:00 Open-Source Ecosystem & PDKs
Open-source tools as a complement; PDK descriptions
12:00 – 13:00 Lunch Break
13:00 – 14:00 Programs for Taping Out ASICs
Overview of Tiny Tapeout (Wokwi, Verilog), Latin/Chip Practice (EDS), and Code-A-Chip (SSCS)
14:00 – 16:00 Community Initiatives & Core Digital Concepts
Chipathon (SSCS), UNIC-CASS, Open Silicon, JKU Platform presentation, Q&A, and core digital flow concepts
16:00 – 16:15 Coffee Break
16:15 – 17:00 Lab 1: Boolean Function Schematic Simulation
Hands-on transistor-level schematic entry and simulation

DAY 2: Physical Layout, Verification & RTL-to-GDSII

Time Session Title & Details
08:30 – 10:30 Lab 2: Boolean Function Layout
Hands-on layout creation for transistor-level design
10:30 – 10:45 Coffee Break
10:45 – 11:30 Lab 2 (Cont.): PEX & Verification
Parasitic extraction (PEX) and post-layout verification of the Boolean function
11:30 – 12:45 Verilog Design & Simulation
Verilog implementation and logic simulation of a 4-bit counter
12:45 – 14:00 Lunch Break
14:00 – 16:00 RTL-to-GDSII Flow & Tapeout Integration
Running the complete RTL-to-GDSII flow for the counter and integrating it onto the Tiny Tapeout platform

Participant Prerequisites & Eligibility

To ensure an optimal hands-on learning experience, applicants must meet the following prerequisites:

  • Language Proficiency: Advanced English (the course is fully delivered in English).
  • Technical Knowledge: Basic understanding of microelectronics and semiconductor principles, including transistors (BJT/FET) and CMOS technology.
  • Software Skills: Working knowledge of Linux operating systems, a scripting language, and Hardware Description Languages (HDL / Verilog).

What Selected Participants Receive

Supported participants selected for the workshop will receive:

  • Full Course & Certificate: Access to the complete 2-day IC design workshop and an official Certificate of Completion.
  • Fabricated Microchip: One physical manufactured chip per qualifying design, sponsored by the Open Silicon Initiative and produced via Tiny Tapeout.
  • Accommodation: 3 nights of shared hotel accommodation in Kuching.
  • Meals: Provided lunch and coffee breaks during the workshop days.
  • Conference Networking: Opportunity to attend IEEE ICM 2026 and engage with global semiconductor experts.

Note: Participant travel, visa fees, airport transfers, dinners, incidentals, and medical expenses are not included

Sponsors & Organizing Partners

Ready to Join?

Submit your application today to secure your spot.

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