Standardization - IEEE P3468 Chiplet Interface Circuit Standard development and vision
December 2026
Borneo Cultures Museum
10:00 AM Till 12:30 PM
December 2026 | At ICM 2026
| Time | Activity |
|---|---|
| 10:00 AM – 10:10 AM | Opening Ceremony Qinfen Hao, IEEE P3468 Chair, Chinese Academy of Sciences |
| 10:10 AM – 10:45 AM | IEEE P3468 Chiplet Interface Circuit Standard: Overview & Vision Qinfen Hao, IEEE P3468 Chair, Chinese Academy of Sciences |
| 10:45 AM – 11:15 AM | Crosstalk Cancellation Technology for High-density, High-Speed Die-to-Die Interconnects Yuanlin Nong, Nanjing University |
| 11:15 AM – 11:45 AM | Research on Compatibility and Testability Technologies for High-Speed, High-Density Interconnections Prof. Xiaoteng Zhao, Xidian University (Virtual) |
| 11:45 AM – 12:20 PM | AI-Driven Chiplet Design: Challenge of Accelerating Innovation Through Open Source EDA BoonChong Ang, Intel |
| 12:20 PM – 12:30 PM | Closing Ceremony BoonChong Ang, Intel |
This opening keynote introduces the motivation, scope, and roadmap of the IEEE P3468 Chiplet Interface Circuit standard. It explains why a unified Compatible IO physical layer — capable of operating in both single-ended and differential modes through one transceiver — is needed to bridge fragmented die-to-die interfaces (UCIe, OIF CEI, HBM). The talk outlines the layered architecture, target application scenarios, and the standardization challenges of multi-vendor interoperability in the AI era.
Qinfen Hao obtained his Ph.D. in System Architecture from the Institute of Computing Technology, Chinese Academy of Sciences (CAS) in 2001. He is currently a Professor at the University of the Chinese Academy of Sciences and Director of the Interconnect Technology Laboratory of ICT, CAS. He has pioneered China's first teraflops high-performance computers, first 32-way high-end SMP servers, first cache-coherence interconnect chips in SMP servers, and the first ARM processor in China. He has published more than 50 research papers with over 100 granted patents and has twice won the second prize of the Chinese National Science and Technology Progress Award. He chairs the IEEE P3468 Chiplet Interface Circuit Standard Working Group.
As die-to-die (D2D) interconnects continue to evolve toward higher density and higher speed, crosstalk is gradually becoming the dominant issue, more prominent than insertion loss. This lecture focuses on crosstalk cancellation technologies for high-density, high-speed D2D interconnects. It first analyzes crosstalk under D2D channel conditions. It then introduces key technical approaches and engineering practices for crosstalk cancellation from the perspectives of channel layout optimization, coding methods, and XTC circuits. Finally, in conjunction with the evolution of relevant standards, it discusses the standardization requirements and development directions of crosstalk cancellation technologies.
Yuanlin Nong is currently pursuing the Ph.D. degree in electrical engineering with Nanjing University, Nanjing, China. His research interests include high-speed wireline transceivers for die-to-die chiplets and memory interfaces.
This talk details the Compatible IO dual-mode PHY at the heart of P3468. It covers the shared-core, mode-switched transceiver supporting single-ended NRZ (2–64 Gb/s) and differential NRZ/PAM4 (56–112 Gb/s) through a high-bandwidth (>32–45 GHz) SE/differential MUX, together with electrical specifications, the configurable VM/CM hybrid driver, and simultaneous bidirectional (SBD) signaling for ~2× bandwidth-density improvement.
Xiaoteng Zhao leads the Physical Layer design of the IEEE P3468 standard, covering the dual-mode PHY architecture, simultaneous bidirectional (SBD) signaling, cross-voltage/cross-process adaptation, and signal integrity. His work focuses on high-speed mixed-signal transceiver design for chiplet interconnects.
The exponential growth of AI and HPC workloads has outpaced traditional transistor scaling, driving a strategic shift toward heterogeneous chiplet architectures and advanced packaging. To support this, open-source Electronic Design Automation (EDA) tools offer a transformative pathway by reducing costs and enabling rapid architectural exploration. However, production adoption faces significant hurdles, including limited advanced-node PDK access, analog tool immaturity, and a lack of formal signoff certification. Consequently, this presentation advocates for a hybrid design methodology: leveraging open-source EDA for early-stage profiling and innovation, while relying on commercial tools for final production signoff. Ultimately, accelerating semiconductor innovation requires coordinated industry efforts to standardize interfaces, validate open-source flows, and build a collaborative, reusable chiplet ecosystem.
Ang Boon Chong was born in Penang, Malaysia, in 1978. He received the B.E. degree in microelectronic engineering from Universiti Putra Malaysia, Malaysia, in 2002, the M.B.A. degree from Open University Malaysia, Malaysia, in 2014, and the D.B.A. degree from UNITAR International University, Malaysia, in 2026. He is currently a Technical Lead with Intel Malaysia, where his work focuses on the evaluation of advanced nodes and methodologies. An active contributor to his field, Dr. Ang has authored over 80 papers, white papers, and books, and has delivered invited talks in eight countries. He is also a Senior Member of the IEEE.